The present application relates to a semiconductor structure and a method of forming the same. More particularly, the present application relates to an interconnect structure containing a self-formed metal nitride liner located on a nitrogen-enriched dielectric surface of an interconnect dielectric material layer as well as a method of forming the same.
Generally, semiconductor devices include a plurality of circuits that form an integrated circuit (IC) fabricated on a semiconductor substrate. A complex network of signal paths will normally be routed to connect the circuit elements distributed on the surface of the substrate. Efficient routing of these signals across the device requires formation of multilevel or multilayered schemes, such as, for example, single or dual damascene wiring structures. The wiring structure, which may also be referred to as an interconnect structure, typically includes copper, Cu, since Cu based interconnects provide higher speed signal transmission between large numbers of transistors on a complex semiconductor chip as compared with aluminum, Al, based interconnects.
Within a typical interconnect structure, metal vias run perpendicular to the semiconductor substrate and metal lines run parallel to the semiconductor substrate. Further enhancement of the signal speed and reduction of signals in adjacent metal lines (known as “crosstalk”) are achieved in today's IC product chips by embedding the metal lines and metal vias (e.g., electrical conducting structures) in a dielectric material having a dielectric constant of less than 4.0.
With the continual scaling of the feature sizes, the volume fraction occupied by a metal liner within an opening used to accommodate an electrical conducting structure dramatically increases and degrades the circuit performance. There is thus a need for providing a method to maximize the electrical conducting structure volume fraction by eliminating or reducing the metal liner from the opening.